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Post by Pruthvi Bharadwaj on Sat Jul 19, 2008 11:38 pm

* Explain the working of a MOSFET.

MOSFETs come in four different types. They may be enhancement or depletion mode, and they may be n-channel or p-channel. For this application we are only interested in n-channel enhancement mode MOSFETs, and these will be the only ones talked about from now on. There are also logic-level MOSFETs and normal MOSFETs. The only difference between these is the voltage level required on the gate.

Unlike bipolar transistors that are basically current-driven devices, MOSFETs are voltage-controlled power devices. If no positive voltage is applied between gate and source the MOSFET is always non-conducting. If we apply a positive voltage UGS to the gate we'll set up an electrostatic field between it and the rest of the transistor. The positive gate voltage will push away the 'holes' inside the p-type substrate and attracts the moveable electrons in the n-type regions under the source and drain electrodes. This produces a layer just under the gate's insulator through which electrons can get into and move along from source to drain. The positive gate voltage therefore 'creates' a channel in the top layer of material between oxide and p-Si. Increasing the value of the positive gate voltage pushes the p-type holes further away and enlarges the thickness of the created channel. As a result we find that the size of the channel we've made increases with the size of the gate voltage and enhances or increases the amount of current which can go from source to drain- this is why this kind of transistor is called an enhancement mode device.

* What is body-effect?

Body effect is increase in threshold voltage of a MOS device.

Threshold voltage is determined by the amount of charge in the depletion region. How? Consider an NMOS device. Lets say the source and substrate are grounded and hence have no potential difference. The interface between the source and substrate is a capacitor. For a capacitor, the amount of positive charge on one plate is equal to the amount of negative charge on the other plate i.e. amount of positive charge on the gate must equal the amount of negative charge in the substrate interface area under the gate which is forming the other plate of this capacitor. This region consists of immobile negative ions because it is depleted. So the gate voltage must first equal this negative charge before it can start attracting electrons from the source/drain to form the channel.

What happens if we make the substrate more negative compared to source? The negative voltage on the substrate starts pulling holes towards it. When the holes are gone, the p-type substrate region will be left with immobile negative ions. Which means the number of immobile negative ions in the substrate region under the gate has increased. Therefore, the gate volatge must be increased some more in order to equal this negative charge. Only then it can start attracting electrons to form the channel. In effect the threshold voltage has increased.

* What is charge sharing?

Charge sharing is an undesirable signal integrity phenomenon observed most commonly in the domino logic family of digital circuits. The charge sharing problem occurs when the charge which is stored at the output node in the phase is shared among the output or junction capacitances of transistors which are in the evaluation phase. Charge sharing may degrade the output voltage level or even cause erroneous output value.

* What is the basic difference between a latch and a flip-flop?

Both latches and flip-flops are circuit elements whose output depends not only on the current inputs, but also on previous inputs and outputs.

The difference between a latch and a flip-flop is that a latch does not have a clock signal, whereas a flip-flop always does.Latches are asynchronous, which means that the output changes very soon after the input changes.A flip-flop is a synchronous version of the latch.
Latch is a level sensitive device and flip-flop is edge sensitive device. Latch is sensitive to glitches on enable pin, where as flip-flop is immune to gltiches.
Latches take less gates (also less power) to implement then flip-flops.
Latches are faster then flip-flops.

this is how the output of the two will differ:

the output of the latch will be the same as the data input as it does not have a clock signal whereas in a flipflop there would be a delay of one clock cycle to see the output.

* What is the difference between Testing & Verification?

Testing is same as Validation where you just verify the performance of the system without actually getting down to the subsystems.

Verification is process that improves the confidence in Validation by analysing the circuits down to the transistor level.

Pruthvi Bharadwaj

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